PUBLICATIONS | JOURNALS

  1. [6] Sangwoo Kang, Xuehao Mou, Babak Fallahazad, Nitin Prasad, Xian Wu, Amithraj Valsaraj, Hema C. P. Movva, Kyounghwan Kim, Emanuel Tutuc, Leonard F. Register, Sanjay K. Banerjee, “Interlayer Tunnel Field-Effect Transistor (ITFET): Physics, Fabrication and Application,” J Phys D, vol. 50, 383002, 2017.

  2. [5] ‡Sangwoo Kang, ‡Nitin Prasad, Hema C. P. Movva, Amritesh Rai, Kyounghwan Kim, Takashi Taniguchi, Kenji Watanabe, Leonard F. Register, Emanuel Tutuc, Sanjay K. Banerjee, “Effects of Electrode Layer Band Structure on the Performance of Multi-Layer Graphene-hBN-Graphene Interlayer Tunnel Field Effect Transistors,” Nano Letters, vol. 16, no. 8, pp. 4975-4981, August, 2016. DOI: 10.1021/acs.nanolett.6b01646.

  3. [4] Sangwoo Kang, Hema C.P. Movva, Atresh Sanne, Amritesh Rai, and Sanjay K. Banerjee, “Influence of Electron-Beam Lithography Exposure Current Level on the Transport Characteristics of Graphene Field Effect Transistors,” Journal of Applied Physics, vol. 119, no. 12, pp. 124502, March 2016.

  4. [3] ‡Sangwoo Kang, ‡Babak Fallahazad, Kayoung Lee, Hema Movva, Kyounghwan Kim, Chris M. Corbet, Takashi Taniguchi, Kenji Watanabe, Luigi Colombo, Leonard F. Register, Emanuel Tutuc, Sanjay K. Banerjee, “Bilayer Graphene-Hexagonal Boron Nitride Heterostructure Negative Differential Resistance Interlayer Tunnel FET,” IEEE Electron Device Letters, vol. 36, no. 4, pp. 405-407, April 2015.

  5. [2] ‡Babak Fallahazad, ‡Kayoung Lee, ‡Sangwoo Kang, Jiamin Xue, Stefano Larentis, Christopher Corbet, Kyounghwan Kim, Hema C. P. Movva, Takashi Taniguchi, Kenji Watanabe, Leonard F. Register, Sanjay K. Banerjee, Emanuel Tutuc, “Gate-Tunable Resonant Tunneling in Double Bilayer Graphene Heterostructures,” Nano Letters, vol. 15, no. 1, pp. 428-433, January 2015.

  6. [1] Sangwoo Kang, Dae-Hwan Kim, Il-Han Park, Jin-Ho Kim, Joung-Eob Lee, Jong Duk Lee, and Byung-Gook Park, “Self-Aligned Dual-Gate Single-Electron Transistors,” Japanese Journal of Applied Physics, Vol. 47, No. 4, pp. 3118-3122, April 2008.

  7. [12] Sagnik Dey, Sangwoo Kang, Sanjay K. Banerjee, “Scaling CMOS to Nanoscale: Beyond the Planar Bulk Silicon MOSFET,” in Comprehensive Semiconductor Science and Technology, Vol. 5, 2019 (in press)

  8. [11] Omar B. Mohammed, Hema C. P. Movva, Sangwoo Kang, Chris M. Corbet, Leonard F. Register, Emanuel Tutuc, Sanjay K. Banerjee, “ReS2-Based Interlayer Tunnel Field Effect Transistor,” in preparation for submission to Nano Letters.

  9. [10] Kyounghwan Kim, Matthew Yankovitz, Babak Fallahazad, Sangwoo Kang, Hema C. P. Movva, Shengqiang Huang, Stefano Larentis, Chris M. Corbet, Takashi Taniguchi, Kenji Watanabe, Sanjay K. Banerjee, Brian J. LeRoy, Emanuel Tutuc, “Van der Waals Heterostructures with High Accuracy Rotational Alignment,” Nano Letters, vol. 16, no. 3, pp. 1989-1995, March 2016.

  10. [9] Hema CP Movva, Amritesh Rai, Sangwoo Kang, Kyounghwan Kim, Babak Fallahazad, Takashi Taniguchi, Kenji Watanabe, Emanuel Tutuc, Sanjay K Banerjee, “High-Mobility Holes in Dual-Gated WSe2 Field-Effect Transistors,” ACS Nano, vol. 9, no. 10, pp. 10402-10410, October 2015.

  11. [8] Amritesh Rai, Amithraj Valsaraj, Hema CP Movva, Anupam Roy, Rudresh Ghosh, Sushant Sonde, Sangwoo Kang, Jiwon Chang, Tanuj Trivedi, Rik Dey, Samaresh Guchhait, Stefano Larentis, Leonard F Register, Emanuel Tutuc, Sanjay K Banerjee, “Air Stable Doping and Intrinsic Mobility Enhancement in Monolayer Molybdenum Disulfide by Amorphous Titanium Suboxide Encapsulation,” Nano Letters, vol. 15, no. 7, pp. 4329-4336, July 2015.

  12. [7] Atresh Sanne, Hema C. P. Movva, Sangwoo Kang, Connor McClellan, Chris Corbet and Sanjay K. Banerjee, “Poly(methyl methacrylate) as a self-assembled gate dielectric for graphene field-effect transistors,” Applied Physics Letter, vol. 104, 083106, February 2014.

  13. [6] Dong-Seup Lee, Sangwoo Kang, Kwon-Chil Kang, Joung-Eob Lee, Hong-Seon Yang, Jung Han Lee, Sang Hyuk Park, Jung Hoon Lee, Jong-Duk Lee, Hyungcheol Shin, and Byung-Gook Park, " Fabrication and Improved Characteristics of Self-Aligned Dual-Gate Single-Electron Transistors," IEEE Transactions on Nanotechnology, vol.8, no.4, pp.492-497, July 2009.

  14. [5] Sang Hyuk Park, Sangwoo Kang, Seongjae Cho, Dong-Seup Lee, Jung Han Lee, Hong-Seon Yang Kwon-Chil Kang, Joung-Eob Lee, Jong Duk Lee, and Byung-Gook Park, “Recessed Channel Dual Gate Single Electron Transistors (RCDG-SETs) for Room Temperature Operation,” IEICE Transactions on Electronics, Vol. E92-C, No. 5, pp. 647-652, May 2009.

  15. [4] Jang-Gn Yun, Yoon Kim, Il Han Park, Jung Hoon Lee, Sangwoo Kang, Dong-Hua Lee, Seongjae Cho, Doo-Hyun Kim, Gil Sung Lee, Won-Bo Sim, Younghwan Son, Hyungcheol Shin, Jong Duk Lee, and Byung-Gook Park, "Fabrication and characterization of fin SONOS flash memory with separated double-gate structure," Solid-State Electronics, vol. 52, pp. 1498-1504, October 2008.

  16. [3] Hoon Jeong, Yeun Seung Lee, Sangwoo Kang, Il Han Park, Woo Young Choi, Hyungcheol Shin, Jong Duk Lee, and Byung-Gook Park, “Capacitorless Dynamic Random Access Memory Cell with Highly Scalable Surrounding Gate Structure,” Japanese Journal of Applied Physics, Vol. 46, No. 4B, pp. 2143-2147, April 2007.

  17. [2] Seung-Hwan Song, Kyung Rok Kim, Jin Ho Kim, Sangwoo Kang, Kwon Chil Kang, Jong Duk Lee, and Byung-Gook Park, "Negative Differential Transconductance Characteristics and Inter-Band Tunneling Mechanism of Fabricated FITETs," Journal of Korean Physical Society, Vol. 49, Dec. 2006, pp. S790~S794.

  18. [1] Seung-Hwan Song, Kyung Rok Kim, Sangwoo Kang, Jin Ho Kim, Jung Im Huh, Kwon Chil Kang, Ki-Whan Song, Jong Duk Lee, and Byung-Gook Park, "Analytical Modeling of Field-Induced Interband Tunneling-Effect Transistors and Its Application," IEEE Transactions on Nanotechnology, Vol. 5, No. 3, pp. 192-200, May 2006.

  1. ‡ indicates equal contribution

  1. Sangwoo Kang was born in Seoul, South Korea, but lived most of his childhood life abroad in the US and UK. He received his BS and MS degrees in electrical engineering at Seoul National University where he studied CMOS scaling limits and single-electron transistors. He worked at Hynix Semiconductors for four years as a DRAM device engineer focusing on peripheral device development and ramp. He then went on to pursue his Ph D at the University of Texas at Austin where he studied 2D material based tunneling devices. He is currently working as a modeling engineer at Texas Instruments where he is delivering compact device models for embedded and analog products.