Highlights
deliver BSIM/Verilog A based compact models for semiconductor devices
develop Python scripts for silicon and model data analysis
developed Verilog A 1/f noise model for pocket implanted devices
demonstrated graphene-hBN heterostructure 2D tunneling device
3x/2x/1x-nm DRAM peripheral device technology road-mapping
44-nm DRAM peripheral device development and ramp-up
demonstrated room temperature operation of silicon single-electron transistor
Skills
semiconductor device physics, solid state physics, process integration, implementation,
characterization, data analysis and compact modeling
BSIM, Spectre, Verilog A, Cadence Virtuoso, Python, Spotfire, Agilent 4156/B1500,
Cascade/Lakeshore probe stations, semiconductor process and analysis tools,
Synopsys and Silvaco TCAD process/device simulation tools
Interests CMOS scaling, semiconductor industry trends, 2D devices, quantum computing
Experience
2021.10 > Compact Modeling Engineer @ Intel
2017.01 > 2021.10 Compact Modeling Engineer @ Texas Instruments
2016.05 > 2016.08 Compact Modeling Intern @ Texas Instruments
2011.08 > 2016.12 Graduate Research Assistant @ MRC, University of Texas at Austin
2007.08 > 2011.07 Device Engineer @ Hynix Semiconductor
2006.03 > 2007.02 Graduate Research Assistant @ ISRC, Seoul National University
Education
2011.08 > 2016.12 Ph D @ University of Texas at Austin
2005.03 > 2007.02 MS @ Seoul National University
2001.03 > 2005.02 BS @ Seoul National University
Journals
6 first author | 18 total
Conferences
7 first author | 38 total
Citations
154 first author | 1299 total @ 09/14/2022
Patents
1 US | 4 Korean
SUMMARY
Sangwoo Kang was born in Seoul, South Korea, but lived most of his childhood life abroad in the US and UK. He received his BS and MS degrees in electrical engineering at Seoul National University where he studied CMOS scaling limits and single-electron transistors. He worked at Hynix Semiconductors for four years as a DRAM device engineer focusing on peripheral device development and ramp. He then went on to pursue his Ph D at the University of Texas at Austin where he studied 2D material based tunneling devices. He is currently working as a modeling engineer at Texas Instruments where he is delivering compact device models for embedded and analog products.