1. 2017 >               Compact Modeling Engineer @ Texas Instruments, Dallas, TX

  2.                           compact model extraction of semiconductor devices for embedded and analog applications
                              improvement of 1/f noise compact model based on Verilog A
                              Python script development for silicon and model data analysis
                              statistical and mismatch data analysis and compact modeling thereof
                              digital circuit FOM analysis for corner model extraction
                              interaction with design teams for model related trouble-shooting
                              interaction with process integration teams for model target/spread discussions

  3. 2016  >  2016    Compact Modeling Intern @ Texas Instruments, Dallas, TX

  4.                           compact 1/f noise model development using Verilog A and Spectre

  5. 2011  >  2016    Research Assistant @ Microelectronics Research Center (MRC), Austin, TX

  6.   demonstrated graphene-hBN hetero-structure 2D tunneling FET
      implementation & characterization of graphene tunneling devices and other 2D FETs
      journal review for
            IEEE Journal of the Electron Devices Society
            IEEE Electron Device Letters
            Journal of Vacuum Science and Technology B
            ACS Nano Letters
            NPJ 2D Materials

  7. 2007  >  2011    Device Engineer @ Hynix  Semiconductor Inc., Icheon, Korea

  8.   DRAM Device Technology Team  |  Peripheral Devices
      development and ramp-up of 44-nm DRAM
      reliability improvement for 3x-nm and 2x-nm node
      assessing eSiGe and high-k dielectric for peripheral device application
      evaluation of novel cold and carbon implant technologies
      technology road mapping with ion implant equipment manufacturers

  9. 2006  >  2007    Research Assistant @ Inter-university Semiconductor Research Center, Seoul, Korea

  10.   demonstrated room temperature operation of silicon single-electron transistor
      improvement of fine line patterning capability of electron beam lithography equipment


  1. 2016  >              Texas Instruments Inc.
                              limitations of BSIM models for pocket implanted MOSFETs
                              corner model methodology for digital circuits

  2. 2011  >  2016    University of Texas at Austin
                              novel graphene-based tunneling FET (BiSFET & ITFET) implementation
                              layered two-dimensional heterostructures
                              process induced variations in graphene FETs

  3. 2007  >  2011    Hynix Semiconductor Inc.
    application of high-k dielectrics & eSiGe to DRAM peripheral devices
                              application of novel ion implantation technology to DRAM peripheral devices
                              device reliability of DRAM high voltage peripheral devices

  4. 2004  >  2007    Seoul National University
                              scaling limits of CMOS
                              silicon-based single-electron transistor (SET) implementation

  1. Sangwoo Kang was born in Seoul, South Korea, but lived most of his childhood life abroad in the US and UK. He received his BS and MS degrees in electrical engineering at Seoul National University where he studied CMOS scaling limits and single-electron transistors. He worked at Hynix Semiconductors for four years as a DRAM device engineer focusing on peripheral device development and ramp. He then went on to pursue his Ph D at the University of Texas at Austin where he studied 2D material based tunneling devices. He is currently working as a modeling engineer at Texas Instruments where he is delivering compact device models for embedded and analog products.